1. Field of the Invention
The present invention relates to a pseudo-static memory device and, more particularly, to a pseudo-static random access memory (PSRAM) device internally having dynamic RAM (DRAM) cells and a circuit for automatically carrying out a refresh for the cells, while functioning as a static RAM (SRAM) in appearance.
A PSRAM has been recently developed as a memory having both the advantages of a DRAM, i.e., low cost, and an SRAM, i.e., high integration density, and is widely used in information apparatus such as computers, electronic apparatuses, and the like.
2. Description of the Related Art
A known typical PSRAM device includes an access circuit for internal refresh, an access circuit for external address access, means for selecting either of the access circuits, and a memory cell array. The external address access circuit further includes a circuit for generating a control signal in response to an external signal and a peripheral circuit for carrying out an access to the memory cells in the array in response to the control signal and an address signal. In this case, the address signal is fed to the PSRAM device by another device for feeding the address signal, e.g., a microprocessor. Also, the selecting means generally is arranged to select either the refresh address signal output from the internal refresh access circuit or the external address signal output from the external address access circuit, in accordance with a timing of the input of the address signal.
Therefore, when an internal refresh access is not needed, preferably the external address access operation is carried out as quickly as possible, from the view point of the demands for a high speed operation of the PSRAM device. Therefore, it is necessary for the aforementioned device for feeding the address signal to fed an address signal consisting of a plurality of address bits to the PSRAM device at a high speed. In this case, the following drawback occurs.
In practice the timings of the change in address among the plurality of address bits are not completely uniform; namely, generally a time lag or lead occurs (hereinafter referred to as an address skew). Where the address skew moves outside a permissible range, a drawback occurs in that another memory cell different from the memory cell to be selected, is selected. Therefore, the timing of the address bits must be strictly controlled in the address signal feeding device, and this means that the constitution of the device becomes complicated and the cost thereof rises.
Another PSRAM device is known which employs a low active chip enable signal (CE) as the aforementioned external signal. In the device, in addition to the above drawback, another drawback occurs in that the timing of the application of the address signal must be strictly set in association with the timing of the application of the external signal (CE). That is, there is a disadvantage that only a small allowance is made for the address skew.